The 74LS165 is a 8-bit serial shift register that shifts the data in the direction of QA toward QH when clocked. Parallel-in access to each stage is made available by eight individual, direct data inputs that are enabled by a low level at the shift/load (SH/LD) input. These registers also feature gated clock (CLK) inputs and complementary outputs from the eighth bit. All inputs are diode-clamped to minimize transmission-line effects, thereby simplifying system design.
Clocking is accomplished through a two-input positive-NOR gate, permitting one input to be used as a clock-inhibit function. Holding either of the clock inputs high inhibits clocking, and holding either clock input low with SH/LD high enables the other clock input. Clock inhibit (CLK INH) should be changed to the high level only while CLK is high. Parallel loading is inhibited as long as SH/LD is high. Data at the parallel inputs are loaded directly into the register while SH/LD is low, independently of the levels of CLK, CLK INH, or serial (SER) inputs.
Features:
Complementary outputs
Direct overriding (data) inputs
Gated clock inputs
Parallel-to-serial data conversion
Typical frequency 35 MHz
Typical power dissipation 105 mW
Note:
16 pin DIP. Actual brand may vary from picture.
Technical Specifications:
Physical
Case/Package
PDIP
Contact Plating
Gold
Mount
Through Hole
Number of Pins
16
Technical
Direction
Unidirectional
Frequency
35 MHz
Input Current
100 µA
Logic Function
Shift Register
Max Operating Temperature
70 °C
Max Supply Voltage
5.25 V
Min Operating Temperature
0 °C
Min Supply Voltage
4.75 V
Nominal Supply Current
42 mA
Number of Bits
8
Number of Bits per Element
8
Number of Circuits
3
Number of Elements
1
Number of Output Lines
1
Operating Supply Voltage
5 V
Propagation Delay
25 ns
Turn-On Delay Time
35 ns
Datasheet:
Download here
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